Simulating an FPGA with Verilator: comprehensive guide

FPGA development is an exciting journey, but it can also be a complex one. With hardware being expensive and sometimes difficult to access, simulation becomes an invaluable tool for developers. In this post, we’ll explore how to simulate an FPGA using Verilator, a powerful and widely-used open-source tool, while writing our design description in VHDL.

Introduction to Verilator and VHDL

Verilator is a high-performance Verilog simulator that allows developers to compile their Verilog designs into C++ or SystemC, enabling efficient simulation and debugging. While Verilator primarily works with Verilog, many developers prefer using VHDL for its strong typing and readability. In this guide, we’ll demonstrate how to leverage Verilator for VHDL-based projects by converting VHDL code into Verilog, making it possible to simulate with Verilator.

Why Simulate with Verilator?

Verilator offers several benefits:

• Speed: It is significantly faster than traditional simulators, making it ideal for large designs.
• Open Source: Being open-source, Verilator is accessible to everyone, and it has a large and active community.
• Flexible: It allows integration with C++/SystemC, enabling powerful testbenches and co-simulation.

Setting Up Verilator

Installation

First, you need to install Verilator. Here’s how to do it on different platforms:

• Linux:

  sudo apt-get install verilator
  

• macOS:

  brew install verilator
  

• Windows:

  You can use Windows Subsystem for Linux (WSL) to install Verilator as you would on a Linux system.

Once installed, verify the installation by running:

verilator --version

Writing Your First VHDL Code

Let’s start with a simple VHDL design—a basic 4-bit counter. Here’s the VHDL code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        clk : in std_logic;
        reset : in std_logic;
        q : out std_logic_vector(3 downto 0)
    );
end entity counter;

architecture behavior of counter is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;

    q <= std_logic_vector(count);
end architecture behavior;

Understanding the Code

• Entity: Defines the interface of the module (inputs and outputs).
• Architecture: Contains the internal logic of the module.
• Process: The process block describes behavior that runs in response to events (e.g., clock edges).

Simulating with Verilator

Converting VHDL to Verilog

Before simulating with Verilator, we need to convert our VHDL code into Verilog. One popular tool for this conversion is GHDL, which can convert VHDL to an intermediate Verilog format.

1. Install GHDL:

   sudo apt-get install ghdl
   

2. Convert VHDL to Verilog:

   ghdl -a counter.vhdl
   ghdl --synth counter > counter.v
   

Simulating with Verilator

With the Verilog file ready, we can now simulate using Verilator.

1. Compile with Verilator:

   verilator -Wall --cc --exe --build counter.v
   

2. Run the Simulation:

   Once compiled, you can run the simulation:

   ./obj_dir/Vcounter
   

Interpreting the Output

Verilator produces a C++ executable that simulates your design. You can add custom C++ code for more sophisticated testbenches, including assertions, checks, and more.

Analyzing the Results

To analyze the results, you might want to visualize waveforms. You can use tools like GTKWave:

1. Install GTKWave:

   sudo apt-get install gtkwave
   

2. Generate Waveform Files:

   Modify your Verilator simulation to dump waveform data:

   VerilatedVcdC* tfp = new VerilatedVcdC;
   top->trace(tfp, 99);
   tfp->open("waveform.vcd");
   

3. View the Waveforms:

   Open the generated waveform.vcd file in GTKWave:

   gtkwave waveform.vcd
   

This allows you to see how your signals change over time, making it easier to debug and verify your design.

Conclusion

Simulating an FPGA with Verilator and writing the description in VHDL is a powerful combination for modern digital design. By following the steps outlined in this guide, you can set up a robust simulation environment, allowing you to catch bugs early and refine your design before committing to hardware.

Now that you have the basics down, you can explore more complex designs and simulations. Whether you’re a hobbyist or a professional, mastering these tools will undoubtedly enhance your FPGA development journey.